Fundamentals of Arbitrary Waveform Generation Ch. 3

Waveform memory is usually SRAM, which is fast and does not need to be refreshed like DRAM. Drawback: Expensive and only room for tens of MSample. Waveform is acessed via adress-counter that periodically resets -> Ring memory.

SRAM is not as fast as high-speeds DACs, so you typically read several points in parallel across a wider bus.

You can also use DRAM, but you need additional processing horsepower to deal with the dynamic refreshing. Gives huge waveforms (GSample). Drawback: Waveforms must have some minimal length for the buffer to be always filled.

Wrap-around-glitches: Reading n samples in parallel means that waveform length should be a multiple of n. This is called the Record Length Granularity. If you neglect this, the AWG may just truncate your waveform.

Memory can be organized in a single memory bank (only one waveform at a time; long switchtime between waveforms), several banks (fast switching, but all limited in size), or segmented memory (one bank, many pointers to start adresses). The latter two allow "sequencing".

Sequencing means iterating over several "segments", with each segment comprising several samples. AWG's may support several stored sequences, and may also allow programmatic control of the sequences using external triggers.

Transitioning between segments may take time. The DAC may play each sample, but the sequencer might take a longer time to be able to jump to another segment again.

If the AWG can store several sequences, it might be possible to define scenarios (playback of sequences in a certain order). Inception.

Sequence Control: "Automatic" = step through the sequence in a predefined order (incl. possible loops). "Conditional": Loop the current sequence until a trigger occurs, then either finish current sequence and go to next, or go to next immediately. "Repeat": Like "Conditional", but don't loop - instead repeat the last sample until the trigger occurs. If you do the latter for all segments, you call this "stepped mode". "Gated Mode": Only run through sequence while trigger is high.

Dynamic Sequence Control: Not only one trigger, but several signals in a parallel bus-configuration can control the sequence playback. Advanced stuff. Limited by bus width (13 bit is typical), and switching time (latency). You can use this to store long binary outpus (by storing 256 sequences that each correspond to one byte).

You can use markers in the waveform to control the synch output. These are either stored as extra bits along the waveform, or in some sort of special stream at reduced timing resolution. Markers are aligned with waveform samples, but waveform samples are not necessarily aligned with features of the waveform (think of a 10 Hz sine sampled with 21 Hz). This can lead to jitter, unless sample-period and signal period are some multiple of each other. Alternatively, you can use a second channel to generate low-jitter clock/synch.

Synchronizing AWG's: Using a 10 MHz refernce for multiple, identical AWG's leads to fixed phase relationships (but the phase of the sampling clock will be arbitrary!!). The AWG's need to be time-aligned for different trigger delays, especially in master/slave configuration, and fine-time-aligned for the sampling clock phase problem. If you use different makes/models of AWG's, they may generate the sampling frequency a bit differently from the clock, which can lead to slow drifts!